Recognition of Hand-Sketched Digital Logic Gates;
| dc.authorscopusid | 56779794200 | |
| dc.authorscopusid | 6506642154 | |
| dc.contributor.author | Gül,N. | |
| dc.contributor.author | Tora,H. | |
| dc.contributor.other | Airframe and Powerplant Maintenance | |
| dc.date.accessioned | 2024-07-05T15:44:29Z | |
| dc.date.available | 2024-07-05T15:44:29Z | |
| dc.date.issued | 2015 | |
| dc.department | Atılım University | en_US |
| dc.department-temp | Gül N., Elektrik - Elektronik Mühendisliʇi Bölümü, Atilim Üniversitesi, Ankara, Turkey; Tora H., Elektrik - Elektronik Mühendisliʇi Bölümü, Atilim Üniversitesi, Ankara, Turkey | en_US |
| dc.description.abstract | Hand-Sketched circuit recognition is a very useful tool in engineering area. Because most of the engineers prefer to design their circuits on the paper firstly. So, this can cause time wasting and some mistakes. In this study, which is based on the solving these kinds of problems, classification and recognition of the handwritten digital logic gates according to their complex and scalar FDs (Fourier Descriptors) is presented. Test results are obtained as 84.3 % accuracy rate for complex FDs, 98.6 % for scalar FDs. Then these results are compared and decided the optimum FDs type for this study. © 2015 IEEE. | en_US |
| dc.identifier.citationcount | 2 | |
| dc.identifier.doi | 10.1109/SIU.2015.7130236 | |
| dc.identifier.endpage | 1924 | en_US |
| dc.identifier.isbn | 978-146737386-9 | |
| dc.identifier.scopus | 2-s2.0-84939175875 | |
| dc.identifier.startpage | 1921 | en_US |
| dc.identifier.uri | https://doi.org/10.1109/SIU.2015.7130236 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.14411/3755 | |
| dc.institutionauthor | Tora, Hakan | |
| dc.language.iso | tr | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.relation.ispartof | 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 - Proceedings -- 2015 23rd Signal Processing and Communications Applications Conference, SIU 2015 -- 16 May 2015 through 19 May 2015 -- Malatya -- 113052 | en_US |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.scopus.citedbyCount | 2 | |
| dc.subject | boundaries of objects | en_US |
| dc.subject | Fourier Descriptors | en_US |
| dc.subject | image processing | en_US |
| dc.subject | object recognition | en_US |
| dc.title | Recognition of Hand-Sketched Digital Logic Gates; | en_US |
| dc.title.alternative | Elle Çizilmiş Sayisal Lojik Kapilarin Taninmasi | en_US |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
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