FPGA üzerinde radar alıcı için eleştirilmiş filtrenin uygulaması
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Date
2018
Authors
Özbek, Mehmet Efe
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Open Access Color
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Abstract
Bu tez, genelolarak radar alıcısını ve spesifik olarak eşleştirilmiş filtreyi ve bu filtrenin FPGA üzerinde uygulanmasını incelemektedir.Birçok örnekte pratik uygulaması olmamasına rağmen, radarın temel konsepti nispeten basittir. Radar elektromanyetik enerjiyi yaymak ve yansıtıcı nesnelerden (hedeflerden) geri dönen sinyalı tespit ederek çalışır. Eko sinyalinin doğası, konum, hızvebelki de boyut gibi hedef hakkında bilgi sağlar.Radar bilgilerinin kalitesini karıştırabilecek ve ya azaltabilecek birçok istenmeyen eko ve müdahale kaynakları vardır. Eşleştirilen Filtre, radarın etraftaki hedefleri başarıyla algılayabilmesi için alınan ekoların SNR'sini artırarak yansıyan sinyalin dağınık ve istenmeyen ekolardan ayrılmasına yardımcı olan bir filtredir. FPGA, özellikle dijital sistem tasarımında yüksek kalitesi ve işlem hızı nedeniyle bu çalışma için bir platform olarak seçilmiştir. Bu çalışmada, Eşleştirilmiş filtre, Verilog dilini kullanılarak FPGA üzerinde uygulanmaktadır.MATLAB da, tasarımı test etmeye yankı sinyallerini oluşturmak için kullanılmıştır.Bu çalışma boyunca, seçilen bütün araçların ve dilin bu pratik çalışma için uygun olduğu açıkça görülmüştür.
The underlying thesis scouts about a radar receiver in general and the Matched Filter and the implementation of this filter on the field programmable gate array FPGA. The practical implementation of the radar system is not as simple as its basic concept might seem. The Radar is operated by detection of the echo which is returned from reflecting objects (targets) and radiating the electromagnetic energy.The information about the target is provided by the nature of the echo signal such as position, velocity, and perhaps size. Several sources exist which are able to affect and confuse the quality of the radar these include undesired interference and echo The Matched Filter is a kind of filter helps to separate the reflected signal from the clutters and undesired echoes by increasing the SNR of the received echo in order to give the radar high ability to detect the targets successfully. The FPGA have been chosen as a platform for this work because of its high quality and speed in processing especially in digital systems design. In this work, the Matched filter is implemented on FPGA by using the Verilog language and MATLAB for generating the echo signals. Throughout this study, it was clearly shown that all the selected tools and language are suitable for this practical work.
The underlying thesis scouts about a radar receiver in general and the Matched Filter and the implementation of this filter on the field programmable gate array FPGA. The practical implementation of the radar system is not as simple as its basic concept might seem. The Radar is operated by detection of the echo which is returned from reflecting objects (targets) and radiating the electromagnetic energy.The information about the target is provided by the nature of the echo signal such as position, velocity, and perhaps size. Several sources exist which are able to affect and confuse the quality of the radar these include undesired interference and echo The Matched Filter is a kind of filter helps to separate the reflected signal from the clutters and undesired echoes by increasing the SNR of the received echo in order to give the radar high ability to detect the targets successfully. The FPGA have been chosen as a platform for this work because of its high quality and speed in processing especially in digital systems design. In this work, the Matched filter is implemented on FPGA by using the Verilog language and MATLAB for generating the echo signals. Throughout this study, it was clearly shown that all the selected tools and language are suitable for this practical work.
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Elektrik ve Elektronik Mühendisliği, Doppler radarı, Electrical and Electronics Engineering, Elektronik haberleşme, Doppler radar, FPGA, Electronic communication, FPGA, Mantıksal programlama, Logic programming
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68