Kiliç, HÖktem, LComputer Engineering2024-07-052024-07-05200578039060110.1109/VDAT.2005.15000582-s2.0-33745454065https://doi.org/10.1109/VDAT.2005.1500058https://hdl.handle.net/20.500.14411/1219Kilic, Hurevren/0000-0002-9058-0365; KILIC, HUREVREN/0000-0003-2647-8451An efficient low-power Test Pattern Generator (TPG) design for Built-In Self-Test (BIST) is introduced. The approach uses the Non-Uniform Cellular Automata (NUCA) model. For our purpose, we designed a polynomial-time algorithm that converts the test pattern generation problem into the classical combinatorial problem called Minimum Set Covering (MSC) which is known to be NP-Complete. Solutions to the MSC problems give the low-power design topology for the test pattern sequence. Comparative analysis of the experimental results showed that even though the obtained designs lack in wiring uniformity they are promising in terms of overall performance criteria based on fault-coverage, test length, used area and dynamic power consumed.eninfo:eu-repo/semantics/closedAccess[No Keyword Available]Conference Object212215WOS:0002339853000558